1. Technical Field
The present invention is concerned with an integrated circuit chip carrier assembly. More particularly, the present invention is concerned with adhering a laminate chip carrier to a stiffener. Moreover, the present invention is concerned with a method for fabricating the integrated circuit chip carrier assembly.
2. Background of Invention
Packaging techniques for integrated circuits have developed with an emphasis on miniaturization. Improved methods enable integrating millions of transistor circuit elements into single integrated semiconductor embodied circuits or chips, and has resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass producible packages. Forming an electronic system requires combining a plurality of integrated circuits and electrically connecting integrated circuits together. Once connected, other devices such as keyboards, video monitors and printers may be connected to and utilized with the electronic system.
In order to establish this interconnection, conductive paths must be made available to connect the internal circuitry of the integrated circuit chip to external system electrical circuits. For example, the integrated circuit package contains conductors referred to as xe2x80x9cbond fingersxe2x80x9d that are interconnected to bond pads of an integrated circuit wafer by, for example, wire bonding or other known techniques. The bond fingers in turn are connected to integrated circuit package pins that are used to connect to printed circuit boards or cards. Ball grid arrays are used for achieving a high density of external chip connections to be made as compared to other package integrated circuits having leads extending from the package.
In certain structures, a stiffener is joined to a printed circuit board or laminate circuit element having a cavity in it for receiving an integrated circuit chip. This type of structure can be referred to as a cavity down chip carrier package. The stiffener can be continuous or can have holes or cutouts therein.
In a typical arrangement a metal stiffener such as copper with plated gold on its back side and copper on its other side is joined to the printed circuit board. Typically, an adhesive such as an epoxy adhesive is coated onto the side of the stiffener containing the copper and then partially cured to its B-stage. A chemical process is typically used such as sodium hypochlorite to oxidize the copper prior to adhesive application to promote adhesion.
In addition, the backside of the printed circuit board that is to be joined to the stiffener contains ground planes as well as gold plated circuitry, with the ground planes and circuitry being protected by a solder mask such as Vacrel(copyright). The solder mask is typically vapor blasted for roughening to enhance its adhesive characteristics and then a layer of epoxy is applied to it and then cured to its B-stage. The epoxy provides the adhesion for joining the stiffener to the printed circuit board.
However, this particular technique suffers from two serious problems. In particular, the epoxy, after lamination, has voided areas which tends to induce delamination. Furthermore, the Vacrele reacts with the copper during thermal cycling thereby causing copper oxide to degrade which also results in problems of delamination. A bare cavity requires that no epoxy be in the cavity. The screening process leaves epoxy in the cavity or the epoxy can bleed into the cavity during cure. In addition, the process is not relatively easy to control and depends upon the relative skill of the process operator for achieving success. Also, such technique requires additional interfacing materials.
The present invention overcomes various problems of the prior art including eliminating the need for the chemical treatment such as the sodium hypochlorite on the stiffener and power planes on the printed circuit board. Furthermore, the present invention eliminates the need for a solder mask on the ground planes and circuitry of the printed circuit board that is to be joined to the stiffener.
More particularly, the present invention is concerned with an integrated circuit chip carrier structure that comprises a substrate having electrically conductive regions on at least one major surface thereof. A stiffener is attached to the substrate by a bonding film. The bonding film comprises a dielectric substrate having a thermoset adhesive on both of its major surfaces.
In addition, the present invention is concerned with a method for fabricating an integrated circuit chip carrier assembly which comprises providing a substrate having electrically conductive regions on at least one major surface thereof. A stiffener is attached to the substrate by providing a bonding film located between the substrate and the stiffener. The bonding film comprises a dielectric substrate having a B-stage thermoset adhesive on both of its major surfaces. The adhesive is tack free at normal room temperatures. The structure of the substrate, bonding film and stiffener is laminated and heated to elevated temperatures for achieving the bond between the substrate and stiffener.
Furthermore, the present invention relates to the product obtained by the above disclosed process.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.